Classical semiconductor scaling, typically known as a device shrink, is currently supplemented by embedded stress engineering, using techniques such as stress memorization, or carbon-doped Si for an N-type field effect transistor (NFET) and SiGe for a P-type field effect transistor (PFET). With circuits becoming smaller and faster, improvement in device drive current is becoming more important. Drive current is closely related to gate length, gate capacitance, and carrier mobility. Embedded stressors are being used to speed carrier mobility in transistor channels, enabling higher drive currents.
Stress or strain in a device may have components in three directions, parallel to the metal-oxide-semiconductor (MOS) device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that a bi-axial in-plane, or uni-axial along the channel length direction tensile strain, can improve NMOS (n-channel MOS transistor) performance, and compressive strain parallel to channel length direction can improve PMOS (p-channel MOS transistor) device performance.
For example, NFET transistor performance may be enhanced by stress memorization technique (SMT). In SMT, the NFET active region is amorphized by Ge, Si or Xe implant, then a capping layer is formed over the NFET, it is annealed, (i.e., the transistor is heated to a high temperature, which may be around 650° C. in some embodiments, and then cooled), and the capping layer is removed. The capping layer confines the volume change from amorphized silicon to crystallized silicon during thermal anneal and causes the formation of stacking faults at the NFET active region. These stacking faults induce tensile stress along the channel. As stress is an important factor in transistor performance, it is therefore desirable to have improvements in shallow trench isolation that enhance the effectiveness of stressor regions in a transistor.